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freescale semiconductor data sheet: technical data document number: MPC5200Bds rev. 3, 10/2008 ? freescale semiconductor, inc., 2008. all rights reserved. this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. tepbga?272 27 mm x 27 mm key features are shown below. ? mpc603e series e300 core ? superscalar architecture ? 760 mips at 400 mhz (-40 to +85 o c) ? 16 k-byte instruction cache, 16 k-byte data cache ? double precision fpu ? instruction and data mmu ? standard and critical interrupt capability ? sdram / ddr memory interface ? up to 133-mhz operation ? sdram and ddr sdram support ? 256-mbyte addressing range per cs, two cs available ? 32-bit data bus ? built-in initialization and refresh ? flexible multi-function external bus interface ? supports interfacing to rom/flash/sram memories or other memory mapped devices ? 8 programmable chip selects ? non multiplexed data access using 8/16/32 bit databus with up to 26-bit address ? short or long burst capable ? multiplexed data access usi ng 8/16/32 bit databus with up to 25-bit address ? peripheral component inte rconnect (pci) controller ? version 2.2 pci compatibility ? pci initiator and target operation ? 32-bit pci address/data bus ? 33- and 66-mhz operation ? pci arbitration function ? ata controller ? version 4 ata compatible external interface?ide disk drive connectivity ? bestcomm dma subsystem ? intelligent virtual dma controller ? dedicated dma channels to control peripheral reception and transmission ? local memory (sram 16 kbytes) ? 6 programmable serial controllers (psc) ? uart or rs232 interface ? codec interface for soft modem, master/slave codec mode, i 2 s and ac97 ? full duplex spi mode ? irda mode from 2400 bps to 4 mbps ? fast ethernet controller (fec) ? supports 100mbps ieee 802.3 mii, 10 mbps ieee 802.3 mii, 10 mbps 7-wire interface ? universal serial bus controller (usb) ? usb revision 1.1 host ? open host controller interface (ohci) ? integrated usb hub, with two ports. ? two inter-integrated circuit interfaces (i 2 c) ? serial peripheral interface (spi) ? dual can 2.0 a/b controller (mscan) ? implementation of version 2.0a/b can protocol ? standard and extended data frames ? j1850 byte data link controller (bdlc) ? j1850 class b data communication network interface compatible and iso compatible for low speed (<125 kbps) serial data communications in automotive applications. ? supports 4x mode, 41.6 kbps ? in-frame response (ifr) type s 0, 1, 2, and 3 supported ? systems level features ? interrupt controller supports four external interrupt request lines and 47 internal interrupt sources ? gpio/timer functions up to 56 total gpio pins that support a variety of interrupt/wakeup capabilities. eight gpio pins with timer capability supporting input capture, output compare, and pulse width modulation (pwm) functions ? real-time clock with one-second resolution ? systems protection (watch dog timer, bus monitor) ? individual control of functional block clock sources ? power management: nap, doze, sleep, deep sleep modes ? support of wakeup from low power modes by different sources (gpio, rtc, can) ? test/debug features ? jtag (ieee 1149.1 test access port) ? common on-chip processor (cop) debug port ? on-board pll and clock generation MPC5200B data sheet
MPC5200B data sheet, rev. 3 freescale semiconductor 2 table of contents 1 electrical and thermal characteristics . . . . . . . . . . . . . . . . . . .4 1.1 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . .4 1.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . .4 1.1.2 recommended operating conditions . . . . . . . . .4 1.1.3 dc electrical specifications. . . . . . . . . . . . . . . . .5 1.1.4 electrostatic discharge . . . . . . . . . . . . . . . . . . . .7 1.1.5 power dissipation . . . . . . . . . . . . . . . . . . . . . . . .7 1.1.6 thermal characteristics. . . . . . . . . . . . . . . . . . . .9 1.2 oscillator and pll electrical ch aracteristics . . . . . . . .10 1.2.1 system oscillator electr ical characteristics . . .11 1.2.2 rtc oscillator electrical characteristics . . . . . .11 1.2.3 system pll electrical characteristics. . . . . . . .11 1.2.4 e300 core pll electrical characteristics . . . . .11 1.3 ac electrical characteristics. . . . . . . . . . . . . . . . . . . . .12 1.3.1 ac test timing conditions: . . . . . . . . . . . . . . . .12 1.3.2 ac operating frequency data. . . . . . . . . . . . . .13 1.3.3 clock ac specifications. . . . . . . . . . . . . . . . . . .13 1.3.4 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.3.5 external interrupts . . . . . . . . . . . . . . . . . . . . . . .15 1.3.6 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.3.7 pci. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.3.8 local plus bus . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.3.9 ata. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 1.3.10 ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 1.3.11 usb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 1.3.12 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 1.3.13 mscan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 1.3.14 i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.3.15 j1850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 1.3.16 psc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 1.3.17 gpios and timers . . . . . . . . . . . . . . . . . . . . . . 54 1.3.18 ieee 1149.1 (jtag) ac specifications . . . . . . 56 2 package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.1 package parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.2 mechanical dimensions. . . . . . . . . . . . . . . . . . . . . . . . 58 2.3 pinout listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3 system design information . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.1 power up/down sequencing . . . . . . . . . . . . . . . . . . . . 64 3.1.1 power up sequence. . . . . . . . . . . . . . . . . . . . . 65 3.1.2 power down sequence . . . . . . . . . . . . . . . . . . 65 3.2 system and cpu core avdd power supply filtering. 65 3.3 pull-up/pull-down resistor requirements . . . . . . . . . . 65 3.3.1 pull-down resistor r equirements for test pins65 3.3.2 pull-up requirements for the pci control lines 66 3.3.3 pull-up/pull-down requirements for mem_mdqs pins (sdram) . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.3.4 .pull-up/pull-down requirements for mem_mdqs pins (ddr 16-bit mode) . . . . . . . . . . . . . . . . . . 66 3.4 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.4.1 jtag_trst . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.4.2 e300 cop/bdm interface . . . . . . . . . . . . . . . . 67 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 70
MPC5200B data sheet, rev. 3 freescale semiconductor 3 figure 1 shows a simplified MPC5200B block diagram. figure 1. simplified block diagram?MPC5200B 603 e300 core sdram/ddr jtag / cop interface reset / clock mscan sdram/ddr commbus local bestcomm sram bus j1850 usb spi i 2 c ethernet psc memory controller generation 16-kbyte dma systems interface unit (siu) real-time clock system functions interrupt controller gpio/timers local plus controller pci bus controller ata host controller 2x 6x 2x 2x
MPC5200B data sheet, rev. 3 4 freescale semiconductor 1 electrical and thermal characteristics 1.1 dc electrical characteristics 1.1.1 absolute maximum ratings the tables in this section describe th e MPC5200B dc electri cal characteristics. table 1 gives the absolute maximum ratings. 1.1.2 recommended operating conditions table 2 gives the recommended operating conditions. table 1. absolute maximum ratings (1) 1 absolute maximum ratings are stress ratings only, and fu nctional operation at the ma ximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage. characteristic sym min max unit specid supply voltage - e300 core and peripheral logic vdd_core ?0.3 1.8 v d1.1 supply voltage - i/o buffers vdd_io, vdd_mem_io ?0.3 3.6 v d1.2 supply voltage - system apll sys_pll_avdd ?0.3 2.1 v d1.3 supply voltage - e300 apll core_pll_avdd ?0.3 2.1 v d1.4 input voltage (vdd_io) vin ?0.3 vdd_io + 0.3 v d1.5 input voltage (vdd_mem_io) vin ?0.3 vdd_mem_io + 0.3 v d1.6 input voltage overshoot vinos ? 1.0 v d1.7 input voltage undershoot vinus ? 1.0 v d1.8 storage temperature range tstg ?55 150 o c d1.9 table 2. recommended operating conditions characteristic sym min (1) max (1) unit specid supply voltage - e300 core and peripheral logic vdd_core 1.42 1.58 v d2.1 supply voltage - standard i/o buffers vdd_io 3.0 3.6 v d2.2 supply voltage - memory i/o buffers (sdr) vdd_mem_io sdr 3.0 3.6 v d2.3 supply voltage - memory i/o buffers (ddr) vdd_mem_io ddr 2.42 2.63 v d2.4 supply voltage - system ap ll sys_pll_avdd 1.42 1.58 v d2.5 supply voltage - e300 apll core_pll_avdd 1.42 1.58 v d2.6
MPC5200B data sheet, rev. 3 freescale semiconductor 5 1.1.3 dc electrical specifications table 3 gives the dc electrical character istics for the MPC5200B at recommended operating conditions (see table 2 ). input voltage - standard i/o buffers vin 0 vdd_io v d2.7 input voltage - memory i/o buffers (sdr) vin sdr 0 vdd_mem_io sdr vd2.8 input voltage - memory i/o buffers (ddr) vin ddr 0vdd_mem_io ddr vd2.9 ambient operating temperature range (2) t a -40 +85 o c d2.10 die junction operating temperature range tj -40 +115 o c d2.12 1 these are recommended and tested operating conditions. pr oper device operation outside these conditions is not guaranteed. 2 maximum e300 core operating frequency is 400 mhz table 3. dc electrical specifications characteristic conditio n sym min max unit specid input high voltage input type = ttl vdd_io/vdd_mem_io sdr v ih 2.0 ? v d3.1 input high voltage input type = ttl vdd_mem_io ddr v ih 1.7 ? v d3.2 input high voltage input type = pci vdd_io v ih 2.0 ? v d3.3 input high voltage input type = schmitt vdd_io v ih 2.0 ? v d3.4 input high voltage sys_xtal_in cv ih 2.0 ? v d3.5 input high voltage rtc_xtal_in cv ih 2.0 ? v d3.6 input low voltage input type = ttl vdd_io/vdd_mem_io sdr v il ?0.8vd3.7 input low voltage input type = ttl vdd_mem_io ddr v il ?0.7vd3.8 input low voltage input type = pci vdd_io v il ?0.8vd3.9 input low voltage input type = schmitt vdd_io v il ? 0.8 v d3.10 input low voltage sys_xtal_in cv il ? 0.8 v d3.11 input low voltage rtc_xtal_in cv il ? 0.8 v d3.12 input leakage current vin = 0 or vdd_io/vdd_io_mem sdr (depending on input type (1) ) i in ?+ 2 a d3.13 input leakage current sys_xtal_in vin = 0 or vdd_io i in ?+ 10 a d3.14 table 2. recommended operating conditions (continued) characteristic sym min (1) max (1) unit specid
MPC5200B data sheet, rev. 3 6 freescale semiconductor input leakage current rtc_xtal_in vin = 0 or vdd_io i in ?+ 10 a d3.15 input current, pullup resistor pullup vdd_io vin = 0 i inpu 40 109 a d3.16 input current, pullup resistor - memory i/o buffers pullup_mem vdd_io_mem sdr vin = 0 i inpu 41 111 a d3.17 input current, pulldown resistor pulldown vdd_io vin = vdd_io i inpd 36 106 a d3.18 output high voltage ioh is driver dependent (2) vdd_io, vdd_io_mem sdr v oh 2.4 ? v d3.19 output high voltage ioh is driver dependent (2) vdd_io_mem ddr v ohddr 1.7 ? v d3.20 output low voltage iol is driver dependent (2) vdd_io, vdd_io_mem sdr v ol ? 0.4 v d3.21 output low voltage iol is driver dependent (2) vdd_io_mem ddr v olddr ? 0.4 v d3.22 dc injection current per pin (3) i cs -1.0 1.0 ma d3.23 capacitance vin = 0v, f = 1 mhz c in ? 15 pf d3.24 1 leakage current is measured with output driv ers disabled and pull-up/pull-downs inactive. 2 see ta bl e 4 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin as listed in table 52 . 3 all injection current is transferred to vdd_io/vdd_io_mem. an external load is required to dissipate this current to maintain the power supply within the specified voltage range. total injection current for all digital input-only and all digita l input/output pins must not exceed 10 ma. exceeding th is limit can cause disruption of normal operation. table 4. drive capability of MPC5200B output pins driver type supply voltage i oh i ol unit specid drv4 vdd_io = 3.3v 4 4 ma d3.25 drv8 vdd_io = 3.3v 8 8 ma d3.26 drv8_od vdd_io = 3.3v - 8 ma d3.27 drv16_mem vdd_io_mem = 3.3v 16 16 ma d3.28 drv16_mem vdd_io_mem = 2.5v 16 16 ma d3.29 pci vdd_io = 3.3v 16 16 ma d3.30 table 3. dc electrical specifications (continued) characteristic conditio n sym min max unit specid
MPC5200B data sheet, rev. 3 freescale semiconductor 7 1.1.4 electrostatic discharge caution this device contains circuitry that protects against damage due to high-static voltage or electrical fields. however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages. operational reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (gnd or v cc ). table 7 gives package thermal char acteristics for this device. 1.1.5 power dissipation power dissipation of the MPC5200B is caused by 3 different compon ents: the dissipation of the in ternal or core digital logic (supplied by vdd_core), the dissipation of the analog ci rcuitry (supplied by sys_pll_avdd and core_pll_avdd) and the dissipation of the io logic (supplied by vdd_io_mem and vdd_io). table 6 details typical measured core and analog power dissipation figures for a range of operating modes. however, the dissipation due to the switching of the io pins can not be given in general, but must be calculated by th e user for each application cas e using the following formula: eqn. 1 where n is the number of output pins switching in a group m, c is the capacitance per pin, vdd_io is the io voltage swing, f is the switching frequency and pioint is the power consumed by the unloaded io stage. the total power consumption of the MPC5200B processor must not exceed the value, which woul d cause the maximum junction temperature to be exceeded. eqn. 2 table 5. esd and latch-up protection characteristics sym rating min max unit specid v hbm human body model (hbm)?jedec jesd22-a114-b 2000 ? v d4.1 v mm machine model (mm)?jedec jesd22-a115 200 ? v d4.2 v cdm charge device model (cdm)?jedec jesd22-c101 500 ? v d4.3 i lat latch-up current at t a =85 o c positive negative +100 -100 ?ma d4.4 i lat latch-up current at t a =27 o c positive negative +200 -200 ?ma d4.5 p io p ioint n m + cvdd _io 2 f = p total p core p analog p io ++ =
MPC5200B data sheet, rev. 3 8 freescale semiconductor table 6. power dissipation core power supply (vdd_core) specid mode sys_xtal/xlb/pci/ipb/core (mhz) unit notes 33/66/33/33/264 33/132/66/132/396 typ typ operational 727.5 1080 mw (1),(2) 1 typical core power is measured at vdd_core = 1.5 v, tj = 25 c 2 operational power is measured while running an entirely ca che-resident program with floating-point multiplication instructions in parallel with a continuous pci transaction via bestcomm. d5.1 doze ? 600 mw (1),(3) 3 doze power is measured with the e300 core in doze m ode, the system oscillator, s ystem pll and core pll are active, all other system modules are inactive d5.2 nap ? 225 mw (1),(4) 4 nap power is measured with the e300 core in nap mode, the system oscillator, system pll and core pll are active, all other system modules are inactive d5.3 sleep ? 225 mw (1),(5) 5 sleep power is measured with the e300 core in sleep mode , the system oscillator, s ystem pll and core pll are active, all other system modules are inactive d5.4 deep-sleep 52.5 52.5 mw (1),(6) 6 deep-sleep power is measur ed with the e300 core in sl eep mode, the system oscillator, system pll, core pll and all other system modules are inactive d5.5 pll power supplies (sys_ pll_avdd, core_pll_avdd) mode typ unit notes ty p i c a l 2 m w (7) 7 typical pll power is measured at sys_pll_ avdd = core_pll_avdd = 1.5 v, tj = 25 c d5.6 unloaded i/o power suppl ies (vdd_io, vdd_mem_io 8 ) 8 io power figures given in the table represent the wors t case scenario. for the vdd_mem_io rail connected to 2.5v the io power is expected to be lower and bounded by the worst case with vdd_me m_io connected to 3.3v. mode typ unit notes ty p i c a l 3 3 m w (9) 9 unloaded typical i/o power is measured in deep-sleep mode at vdd_io = vdd_mem_io sdr = 3.3 v, tj = 25 c d5.7
MPC5200B data sheet, rev. 3 freescale semiconductor 9 1.1.6 thermal characteristics 1.1.6.1 heat dissipation an estimation of the chip -junction temperature, t j , can be obtained from the following equation: t j =t a +(r ja p d ) eqn. 3 where: t a = ambient temperature for the package (oc) r ja = junction to ambient thermal resistance (oc/w) p d = power dissipation in package (w) the junction to ambient thermal resistance is an industry standard value, which provides a quick and easy estimation of thermal performance. unfortunately, there are two va lues in common usage: the value determin ed on a single layer board, and the value obtained on a board with two planes. for pack ages such as the pbga, these values can be different by a factor of two. which value is correct depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. the value obtained on the board with the internal planes is usuall y appropriate if the board has low power dissipa tion and the components are well separated. historically, the thermal resistance has frequently been expres sed as the sum of a junction to case thermal resistance and a ca se to ambient thermal resistance: table 7. thermal resistance data rating board layers sym value unit notes specid junction to ambient natural convection single layer board (1s) r ja 30 c/w (1),(2) 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, po wer dissipation of other components on the board, and board thermal resistance. 2 per semi g38-87 and jedec jesd51-2 with the single layer board horizontal. d6.1 junction to ambient natural convection four layer board (2s2p) r jma 22 c/w (1),(3) 3 per jedec jesd51-6 with the board horizontal. d6.2 junction to ambient (@200 ft/min) single layer board (1s) r jma 24 c/w (1),(3) d6.3 junction to ambient (@200 ft/min) four layer board (2s2p) r jma 19 c/w (1),(3) d6.4 junction to board ? r jb 14 c/w (4) 4 thermal resistance between the die and the printed ci rcuit board per jedec jesd51- 8. board temperature is measured on the top surface of the board near the package. d6.5 junction to case ? r jc 8c/w (5) 5 thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). d6.6 junction to package top natural convection jt 2c/w (6) 6 thermal characterization parameter indicating the tem perature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. d6.7
MPC5200B data sheet, rev. 3 10 freescale semiconductor r ja =r jc +r ca eqn. 4 where: r ja = junction to ambient thermal resistance (oc/w) r jc = junction to case thermal resistance (oc/w) r ca = case to ambient thermal resistance (oc/w) r jc is device related and cannot be influenced by the user. the user controls the thermal environment to change the case to ambient thermal resistance, r ca . for instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the ther mal dissipation on the printed circuit board surrounding the device. this description is most useful fo r ceramic packages with heat sinks where so me 90% of the heat flow is through the case to the heat sink to ambient. for mo st packages, a better model is required. a more accurate thermal model can be constr ucted from the junction to board thermal resistance and the junction to case thermal resistance. the junction to case co vers the situation where a heat sink is used or a substantial amount of heat is dissipated f rom the top of the package. the junc tion to board thermal resistance describes the th ermal performance when most of the heat is conducted to the printed circuit board. this model can be used fo r hand estimations or for a computational fluid dynamics (cfd) thermal model. to determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter ( jt ) can be used to determine the junction temperat ure with a measurement of the temperature at the top center of the package case using the following equation: t j =t t +( jt p d ) eqn. 5 where: t t = thermocouple temperature on top of package (oc) jt = thermal characterization parameter (oc/w) p d = power dissipation in package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40-gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned, so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocoupl e junction and over approximately one mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement erro rs caused by cooling effects of the thermocouple wire. 1.2 oscillator and pll electrical characteristics the MPC5200B system requires a system-level clock input sys_xtal. this clock input may be driven directly from an external oscillator or with a crys tal using the internal oscillator. there is a separate oscillator for the independent real-time clock (rtc) system. the MPC5200B clock generation uses two phase locked loop (pll) blocks. ? the system pll (sys_pll) takes an ex ternal reference frequency and genera tes the internal system clock. the system clock frequency is determined by the external reference frequency and the settings of the sys_pll configuration. ? the e300 core pll (core_pll) generates a master clock for all of the cpu circuitry. th e e300 core clock frequency is determined by the system clock frequency a nd the settings of the core_pll configuration.
MPC5200B data sheet, rev. 3 freescale semiconductor 11 1.2.1 system oscillator electrical characteristics 1.2.2 rtc oscillator electrical characteristics 1.2.3 system pll electrical characteristics 1.2.4 e300 core pll electrical characteristics the internal clocking of the e300 core is generated from and s ynchronized to the system clock by means of a voltage-controlled core pll. table 8. system oscillator electrical characteristics characteristic sym notes min typical max unit specid sys_xtal frequency f sys_xtal 15.6 33.3 35.0 mhz o1.1 oscillator start-up time t up_osc ? ? 10 ms o1.2 table 9. rtc oscillator electrical characteristics characteristic sym notes min typical max unit specid rtc_xtal frequency f rtc_xtal ? 32.768 ? khz o2.1 table 10. system pll specifications characteristic sym notes min typical max unit specid sys_xtal frequency f sys_xtal (1) 1 the sys_xtal frequency and pll configuration bits must be chosen such that the resulting system frequency, cpu (core) frequency, and pll (vco) frequency do not e xceed their respective maximum or minimum operating frequencies. 15.6 33.3 35.0 mhz o3.1 sys_xtal cycle time t sys_xtal (1) 66.6 30.0 28.5 ns o3.2 sys_xtal clock input jitter t jitter (2) 2 this represents total input jitter - short term and long te rm combined - and is guaranteed by design. two different types of jitter can exist on t he input to core_sysclk, systemic and true ran dom jitter. true random jitter is rejected. systemic jitter is passed into and through the pll to the internal clock circuitry. ? ? 150 ps o3.3 system vco frequency f vcosys (1) 250 533 800 mhz o3.4 system pll relock time t lock (3) 3 relock time is guaranteed by design and characterization. pll-relock time is the maximum amount of time required for the pll lock after a stable vdd and core_sysclkare reached during the power-on reset sequence. this specification also applies when the pll has been disa bled and subsequently re-enabled during sleep modes. ? ? 100 so3.5
MPC5200B data sheet, rev. 3 12 freescale semiconductor 1.3 ac electrical characteristics hyperlinks to the indicated timing specification sections are provided below. 1.3.1 ac test timing conditions: unless otherwise noted, all test conditions are as follows: ? ta = -40 to 85 o c ? tj = -40 to 115 o c ? vdd_core = 1.42 to 1.58 v vdd_io = 3.0 to 3.6 v table 11. e300 pll specifications characteristic sym notes min typical max unit specid e300 frequency f core (1) 1 the xlb_clk frequency and e300 pll configuration bits must be chosen such that the resulting system frequencies, cpu (core) frequency, and e300 pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies in ta b l e 1 2 . 50 ? 550 mhz o4.1 e300 cycle time t core (1) 2.85 ? 40.0 ns o4.2 e300 vco frequency f vcocore (1) 400 ? 1200 mhz o4.3 e300 input clock frequency f xlb_clk 25 ? 367 mhz o4.4 e300 input clock cycle time t xlb_clk 2.73 ? 50.0 ns o4.5 e300 input clock jitter t jitter (2) 2 this represents total input jitter - short term and long te rm combined - and is guaranteed by design. two different types of jitter can exist on t he input to core_sysclk, systemic and true ran dom jitter. true random jitter is rejected. systemic jitter is passed into and through the pll to the internal clock circuitry. ? ? 150 ps o4.6 e300 pll relock time t lock (3) 3 relock time is guaranteed by design and characterization. pll-relock time is the maximum amount of time required for the pll lock after a stable vdd and core_sysclk are reached during the power-on reset sequence. this specification also applies when the pll has been disa bled and subsequently re-enabled during sleep modes. ? ? 100 so4.7 ? ac operating frequency data ? usb ? clock ac specifications ? spi ?resets ?mscan ? external interrupts ? i 2 c ? sdram ? j1850 ?pci ?psc ? local plus bus ? gpios and timers ? ata ? ieee 1149.1 (jtag) ac specifications ? ethernet
MPC5200B data sheet, rev. 3 freescale semiconductor 13 ? input conditions: all inputs: tr, tf <= 1 ns ? output loading: all outputs: 50 pf 1.3.2 ac operating frequency data table 12 provides the operating frequency information for the MPC5200B. 1.3.3 clock ac specifications figure 2. timing diagram?sys_xtal_in table 12. clock frequencies min max units specid 1 e300 processor core ? 400 mhz a1.1 2 sdram clock ? 133 mhz a1.2 3 xl bus clock ? 133 mhz a1.3 4 ip bus clock ? 133 mhz a1.4 5 pci / local plus bus clock ? 66 mhz a1.5 6 pll input range 15.6 35 mhz a1.6 table 13. sys_xtal_in timing sym description min max units specid t cycle sys_xtal_in cycle time. (1) 1 caution ?the sys_xtal_in freq uency and system pll_cfg[0-6 ] settings must be chosen such that the resulting system frequencies do not exceed their respective maxi mum or minimum operating frequencies. see the MPC5200B user manual. 28.6 64.1 ns a2.1 t rise sys_xtal_in rise time. ? 5.0 ns a2.2 t fall sys_xtal_in fall time. ? 5.0 ns a2.3 t duty sys_xtal_in duty cycle (measured at v m ). (2) 2 sys_xtal_in duty cycle is measured at v m . 40.0 60.0 % a2.4 cv ih sys_xtal_in input voltage high 2.0 ? v a2.5 cv il sys_xtal_in input voltage low ? 0.8 v a2.6 t fall t rise t cycle sysclk t duty t duty cv ih cv il v m v m v m
MPC5200B data sheet, rev. 3 14 freescale semiconductor 1.3.4 resets the MPC5200B has three reset pins: ? porreset - power on reset ?hreset - hard reset ?sreset - software reset these signals are asynchronous i/o signals an d can be asserted at any time. the input side uses a schmitt trigger and requires the same input characteristics as other MPC5200B inputs, as specified in the dc electrical specifications section. table 14 specifies the pulse widths of the reset inputs. for porreset the value of the minimum pulse width re flects the power on se quence. if porreset is asserted afterwards its minimum pulse width equals the minimum given for hreset related to the same reference clock. the t vdd_stable describes the time which is needed to get all power supplies stable. for t lock, refer to the oscillator/pll section of this specification for further details. for t up_osc, refer to the oscillator/pll section of this specification for further details. following the deassertion of porreset , hreset and sreset remain low for 4096 reference clock cycles. the deassertion of hreset for at least the minimum pulse width forces the internal resets to be active for an additional 4096 clock cycles. note as long as vdd is not stable the hreset output is not stable. note make sure that the porreset does not carry any glitches. the MPC5200B has no filter to prevent them from getting into the chip. hreset and sreset must have a monotonous rise time. the assertion of hreset becomes active at powe r on reset without any sys_xtal clock. table 14. reset pulse width name description min pulse width max pulse width reference clock specid porreset power on reset t vdd_stable +t up_osc +t lock ? sys_xtal_in a3.1 hreset hardware reset 4 clock cycles ? sys_xtal_in a3.2 sreset software reset 4 cl ock cycles ? sys_xtal_in a3.3 table 15. reset rise/fall timing description min max unit specid porreset fall time ? 1 ms a3.4 porreset rise time ? 1 ms a3.5 hreset fall time ? 1 ms a3.6 hreset rise time ? 1 ms a3.7 sreset fall time ? 1 ms a3.8 sreset rise time ? 1 ms a3.9
MPC5200B data sheet, rev. 3 freescale semiconductor 15 for additional information, see the MPC5200B user manual. 1.3.4.1 reset configuration word during reset (hreset and porreset ) the reset configuration word is latched in the related reset configuration word register with each rising ed ge of the sys_xtal signal. if both resets (hreset and porreset ) are inactive (high), the contents of this register are locked immediately wi th the sys_xtal clock (see figure 3 ). figure 3. reset configuration word locking note beware of changing the values on the pins of the reset configuration word after the deassertion of porreset . this may cause problems because it may change the internal clock ratios and so extend the pll locking process. 1.3.5 external interrupts the MPC5200B provides three different kinds of external interrupts: ? four irq interrupts ? eight gpio interrupts with simple interrupt capability (not available in power-down mode) ? eight wakeup interrupts (special gpio pins) the propagation of these three ki nds of interrupts to the core is shown in the following graphic: sample sample sample sample sample sample sample sample sample sample lock rst_cfg_wrd hreset porreset sys_xtal 4096 clocks
MPC5200B data sheet, rev. 3 16 freescale semiconductor figure 4. external interrupt scheme due to synchronization, prioritization, and mapping of external interrupt sources, the propagation of external interrupts to th e core processor is delayed by several ip_clk clock cycles. the following table specifies the interrupt latencies in ip_clk cycles. the ip_clk frequency is programmable in the clock distribution module (see table 16 ). notes: 1) the frequency of ip_clk depends on regi ster settings in clock distribution module. see the MPC5200B user manual. table 16. external interrupt latencies interrupt type pin name clock cycles reference clock core interrupt specid interrupt requests irq0 10 ip_clk critical (cint) a4.1 irq0 10 ip_clk normal (int) a4.2 irq1 10 ip_clk normal (int) a4.3 irq2 10 ip_clk normal (int) a4.4 irq3 10 ip_clk normal (int) a4.5 standard gpio interrupts gpio_psc3_4 12 ip_clk normal (int) a4.6 gpio_psc3_5 12 ip_clk normal (int) a4.7 gpio_psc3_8 12 ip_clk normal (int) a4.8 gpio_usb_9 12 ip_clk normal (int) a4.9 gpio_ethi_4 12 ip_clk normal (int) a4.10 gpio_ethi_5 12 ip_clk normal (int) a4.11 gpio_ethi_6 12 ip_clk normal (int) a4.12 gpio_ ethi_7 12 ip_clk normal (int) a4.13 gpio wakeup interrupts gpio_ psc1_4 12 ip_clk normal (int) a4.15 gpio_psc2_4 12 ip_clk normal (int) a4.16 gpio_psc3_9 12 ip_clk normal (int) a4.17 gpio_ethi_8 12 ip_clk normal (int) a4.18 gpio_irda_0 12 ip_clk normal (int) a4.19 dgp_in0 12 ip_clk normal (int) a4.20 dgp_in1 12 ip_clk normal (int) a4.21 8 gpios 8 gpios gpio wakeup gpio std irq0 irq1 irq2 irq3 pis cint int grouper encoder encoder main interrupt controller core_cint core_int e300 core notes: 1. pis = programmable inputs 2. grouper and encoder functions imply programmability in software 8 8
MPC5200B data sheet, rev. 3 freescale semiconductor 17 2) the interrupt latency descriptions in the table above are re lated to non competitive, non masked but enabled external interr upt sources. take care of interrupt prioritization which may increase the latencies. because all external interrupt signals are synchronized into the internal processor bus clock domain, each of these signals has to exceed a minimum pulse width of more than one ip_clk cycle. notes: 1) the frequency of the ip_clk depends on the register settings in clock distribution module. see the MPC5200B user manual for further information. 2) if the same interrupt occurs a second time while its interr upt service routine has not clear ed the former one, the second interrupt is not recognized at all. besides synchronization, prioritization, and mapping the latency of an external interrupt to the start of its associated interr upt service routine also depends on the following conditions: to get a minimum interrupt service response time, it is recommended to enable the instruction cache and set up the maximum core cloc k, xl bus, and ip bus freque ncies (depending on board design and programming). in addition, it is advisable to execute an in terrupt handler, which has been implemented in assembly code. 1.3.6 sdram 1.3.6.1 memory interface timing -standard sdram read command table 17. minimum pulse width for external interrupts to be recognized name min pulse width max pulse width reference clock specid all external interrupts (irqs, gpios) > 1 clock cycle ? ip_clk a4.22 table 18. standard sdram memory read timing sym description min max units specid t mem_clk mem_clk period 7.5 ? ns a5.1 t valid control signals, address and mba valid after rising edge of mem_clk ?t mem_clk *0.5+0.4 ns a5.2 t hold control signals, address and mba hold after rising edge of mem_clk t mem_clk *0.5 ? ns a5.3 dm valid dqm valid after rising edge of mem_clk ? t mem_clk *0.25+0.4 ns a5.4 dm hold dqm hold after rising edge of mem_clk t mem_clk *0.25-0.7 ? ns a5.5 data setup mdq setup to rising edge of mem_clk ? 0.3 ns a5.6 data hold mdq hold after rising edge of mem_clk 0.2 ? ns a5.7
MPC5200B data sheet, rev. 3 18 freescale semiconductor figure 5. timing diagram?standard sdram memory read timing 1.3.6.2 memory interface timing -standard sdram write command in standard sdram, all signals are act ivated on the mem_clk from the memory controller and captured on the mem_clk clock at the memory device. table 19. standard sdram write timing sym description min max units specid t mem_clk mem_clk period 7.5 ? ns a5.8 t valid control signals, address and mba valid after rising edge of mem_clk ?t mem_clk *0.5+0.4 ns a5.9 t hold control signals, address and mba hold after rising edge of mem_clk t mem_clk *0.5 ? ns a5.10 dm valid dqm valid after rising edge of mem_clk ? t mem_clk *0.25+0.4 ns a5.11 dm hold dqm hold after rising edge of mem_clk t mem_clk *0.25-0.7 ? ns a5.12 data valid mdq valid after rising edge of mem_clk ? t mem_clk *0.75+0.4 ns a5.13 data hold mdq hold after rising edge of mem_clk t mem_clk *0.75-0.7 ? ns a5.14 mem_clk control signals mdq (data) ma (address) note: control signals are composed of ras, cas, mem_we , mem_cs , mem_cs1 and clk_en active nop read nop nop nop nop t hold row column mba (bank selects) t valid t hold t valid t hold t valid dqm (data mask) dm valid dm hold nop data hold data setup
MPC5200B data sheet, rev. 3 freescale semiconductor 19 figure 6. timing diagram?standard sdram memory write timing 1.3.6.3 memory interface timing-ddr sdram read command the sdram memory controller uses a 1/4 period delayed mdqs strobe to capture the mdq data. the 1/4 period delay value is calculated automatically by hardware. table 20. ddr sdram memory read timing sym description min max units specid t mem_clk mem_clk period 7.5 ? ns a5.15 t valid control signals, address and mba valid after rising edge of mem_clk ?t mem_clk *0.5+0.4 ns a5.16 t hold control signals, address and mba hold after rising edge of mem_clk t mem_clk *0.5 ? ns a5.17 data setup setup time relative to mdqs ? 0.4 ns a5.18 data hold hold time relative to mdqs 2.6 ? ns a5.19 mem_clk control signals mdq (data) ma (address) note: control signals are composed of ras, cas, mem_we , mem_cs , mem_cs1 and clk_en active nop write nop nop nop nop nop t hold row column mba (bank selects) data hold data valid t valid t hold t valid t hold t valid dqm (data mask) dm valid dm hold
MPC5200B data sheet, rev. 3 20 freescale semiconductor figure 7. timing diagram?ddr sdram memory read timing mem_clk control signals mdq (data) ma (address) mem_clk mdqs (data strobe) note: control signals signals are composed of ras, cas, mem_we , mem_cs , mem_cs1 and clk_en active nop read nop nop nop nop nop t hold row column mba (bank selects) t valid t hold t valid t hold t valid t data_valid_min t data_valid_max read data t data_sample_min t data_sample_max sample window mdq (data) mdqs (data strobe) t data_valid_min t data_valid_max read data t data_sample_min t data_sample_max sample window sample position a: data are sampled on the expected edge of mem_clk, the mdqs signal indicate the valid data sample position a sample position b sample position b: data are sampled on a later edge of mem_clk, sdram controller is waiting for the vaild mdqs signal 0.5 * t mem_clk
MPC5200B data sheet, rev. 3 freescale semiconductor 21 1.3.6.4 memory interface timi ng-ddr sdram write command figure 8. ddr sdram memory write timing 1.3.7 pci the pci interface on the MPC5200B is designed to pci vers ion 2.2 and supports 33-mhz and 66-mhz pci operations. see the pci local bus specification; the component section specifies the electrical and tim ing parameters for pci components with the intent that components connect directly toge ther whether on the planar or an expansio n board, without any external buffers or other ?glue logic.? parameters ap ply at the package pins, not at expansion board edge connectors. the MPC5200B is always the source of th e pci clk. the clock waveform must be delivered to each 33-mhz or 66-mhz pci component in the system. figure 9 shows the clock waveform and required measurement points for 3.3 v signaling environments. table 22 summarizes the clock specifications. table 21. ddr sdram memory write timing sym description min max units specid t mem_clk mem_clk period 7.5 ? ns a5.20 t dqss delay from write command to first rising edge of mdqs ?t mem_clk +0.4 ns a5.21 data valid mdq valid before rising edge of mdqs 1.0 ? ns a5.22 data hold mdq valid after rising edge of mdqs 1.0 ? ns a5.23 mem_clk control signals mdq (data) mem_clk mdqs (data strobe) note: control signals signals are composed of ras, cas, mem_we , mem_cs , mem_cs1, and clk_en write write write t dqss write datavalid datahold
MPC5200B data sheet, rev. 3 22 freescale semiconductor figure 9. pci clk waveform notes: 1. in general, all 66-mhz pci components must work with any cloc k frequency up to 66 mhz. clk requirements vary depending upon whether the clock frequency is above 33 mhz. 2. rise and fall times are specified in terms of the edge rate meas ured in v/ns. this slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in figure 9 . 3. the minimum clock period must not be violated for any single clock cycle, i. e., accounting for all system jitter. notes: 1. see the timing measurement conditions in the pci local bus specif ication. it is important that all driven signal transitions drive to their voh or vol level within one tcyc. table 22. pci clk specifications sym description 66 mhz 33 mhz units notes specid min max min max t cyc pci clk cycle time 15 30 30 ns (1),(3) a6.1 t high pci clk high time 6 11 ns a6.2 t low pci clk low time 6 11 ns a6.3 ? pci clk slew rate 1.5 4 1 4 v/ns (2) a6.4 ? pci clock jitter (peak to peak) 200 200 ps table 23. pci timing parameters sym description 66 mhz 33 mhz units notes specid min max min max t val clk to signal valid delay - bused signals 26211ns (1),(2),(3) a6.5 t val (ptp) clk to signal valid delay - point to point 26212ns (1),(2),(3) a6.6 t on float to active delay 2 2 ns (1) a6.7 t off active to float delay 14 28 ns (1) a6.8 t su input setup time to clk - bused signals 37ns (3),(4) a6.9 t su (ptp) input setup time to clk - point to point 5 10,12 ns (3),(4) a6.10 t h input hold time from clk 0 0 ns (4) a6.11 t cyc pci clk t low t high 0.4vcc 0.4vcc, p-to-p 0.3vcc 0.5vcc 0.6vcc 0.2vcc (minimum)
MPC5200B data sheet, rev. 3 freescale semiconductor 23 2. minimum times are measured at the package pin with the load ci rcuit, and maximum times are measured with the load circuit as shown in the pci local bus specification. 3. req# and gnt# are point-to-point signals and have different input setup times than do bused signals. gnt# and req# have a setup of 5 ns at 66 mhz. all other signals are bused. 4. see the timing measurement conditions in the pci local bus specification. for measurement and test conditions, see the pci local bus specification. 1.3.8 local plus bus the local plus bus is the external bus interface of the MPC5200B. a maximum of ei ght configurable chip selects (cs) are provided. there are two main modes of operation: non-muxed (legacy and burst) and muxed. the reference clock is the pci clk. the maximum bus frequency is 66 mhz. definition of acronyms and terms: ? ws = wait state ? dc = dead cycle ? lb = long burst ? ds = data size in bytes ? tpcick = pci clock period ? tipbick = ipbi clock period figure 10. timing diagra m?ipbi and pci clock (example ratio: 4:1) 1.3.8.1 non-muxed mode table 24. non-muxed mode timing sym description min max units notes specid t csa pci clk to cs assertion 4.6 10.6 ns a7.1 t csn pci clk to cs negation 2.9 7.0 ns a7.2 t 1 cs pulse width (2+ws)*t pcick (2+ws)*t pcick ns (1) a7.3 t 2 addr valid before cs assertion t ipbick t pcick ns a7.4 t 3 addr hold after cs negation t ipbick -ns (2) a7.5 t 4 oe assertion before cs assertion - 4.8 ns a7.6 t 5 oe negation before cs negation - 2.7 ns a7.7 t 6 rw valid before cs assertion t pcick -nsa7.8 t 7 rw hold after cs negation t ipbick -nsa7.9 t 8 data output valid before cs assertion t ipbick - ns a7.10 t 9 data output hold after cs negation t ipbick - ns a7.11 pci clk ipbi clk t ipbick t pcick
MPC5200B data sheet, rev. 3 24 freescale semiconductor notes: 1. ack can shorten the cs pulse width. wait states (ws) can be programmed in the chip select x regi ster, bit field waitp and waitx. it can be specified from 0 - 65535. 2. in large flash and most graphics mode the shared pci/ata pi ns, used as address lines, are released at the same moment as the cs. this can cause the address to change before cs is deasserted. 3. ack is input and can be used to shorten the cs pulse width. 4. only available in large flash and most graphics mode. 5. only available in most graphics mode. 6. deadcycles are only used, if no arbitration to an other module (ata or pci) of the shared local bus happens. if arbitration happens the bus can be driven within 4 ipb clocks by an other modules. t 10 data input setup before cs negation 8.5 - ns a7.12 t 11 data input hold after cs negation 0 (dc+1)*t pcick ns (6) a7.13 t 12 ack assertion after cs assertion t pcick -ns (3) a7.14 t 13 ack negation after cs negation - t pcick ns (3) a7.15 t 14 ts assertion before cs assertion - 6.9 ns (4) a7.16 t 15 ts pulse width t pcick t pcick ns (4) a7.17 t 16 tsiz valid before cs assertion t ipbick -ns (5) a7.18 t 17 tsiz hold after cs negation t ipbick -ns (5) a7.19 t 18 ack change before pci clock - 2.0 ns (1) a7.20 t 19 ack change after pci clock - 4.4 ns (1) a7.21 table 24. non-muxed mode timing (continued) sym description min max units notes specid
MPC5200B data sheet, rev. 3 freescale semiconductor 25 figure 11. timing diagram?non-muxed mode 1.3.8.2 burst mode table 25. burst mode timing sym description min max units notes specid t csa pci clk to cs assertion 4.6 10.6 ns a7.22 t csn pci clk to cs negation 2.9 7.0 ns a7.23 t 1 cs pulse width (1+ws+4 lb *2*(32/ds))* t pcick (1+ws+4 lb *2*(32/ds)) *t pcick ns (1),(2) a7.24 t 2 addr valid before cs assertion t ipbick t pcick ns a7.25 t 3 addr hold after cs negation -0.7 - ns a7.26 t 4 oe assertion before cs assertion - 4.8 ns a7.27 t 5 oe negation before cs negation - 2.7 ns a7.28 t 6 rw valid before cs assertion t pcick - ns a7.29 t 7 rw hold after cs negation t pcick - ns a7.30 t 8 data setup before rising edge of pci clock 3.6 - ns a7.31 addr data (rd) cs [x] r/w data (wr) oe t 10 t 11 ts t 2 t 6 t 8 t 7 t 4 t 3 t 9 tsiz[1:2] t 5 t 17 t 16 ack t 12 t 13 t 14 t 15 t 1 pci clk t 18 t 19
MPC5200B data sheet, rev. 3 26 freescale semiconductor notes: 1. wait states (ws) can be programmed in the chip select x regi ster, bit field waitp and waitx. it can be specified from 0 - 65535. 2. example: long burst is used, this means the cs rela ted berx and slb bits of the chip select burst control register are set and a burst on the internal xlb is executed. => lb = 1 data bus width is 8 bit. => ds = 8 => 4 1 *2*(32/ 8 ) = 32 => ack is asserted for 32 pci cycles to transfer one cache line. wait state is set to 10. => ws = 10 1+ 10 +32 = 43 => cs is asserted for 43 pci cycles. 3. ack is output and indicates the burst. 4. deadcycles are only used, if no arbitration to an other module (ata or pci) of the shared local bus happens. if arbitration happens the bus can be driven within 4 ipb clocks by an other modules. figure 12. timing diagram?burst mode t 9 data hold after rising edge of pci clock 0-nsa7.32 t 10 data hold after cs negation 0 (dc+1)*t pcick ns (4) a7.33 t 11 ack assertion after cs assertion - (ws+1)*t pcick ns a7.34 t 12 ack negation before cs negation - 7.0 ns (3) a7.35 t 13 ack pulse width 4 lb *2*(32/ds)*t pcick 4 lb *2*(32/ds)*t pcick ns (2),(3) a7.36 t 14 cs assertion after ts assertion - 2.5 ns a7.37 t 15 ts pulse width t pcick t pcick ns a7.38 table 25. burst mode timing (continued) sym description min max units notes specid addr data (rd) cs [x] r/w oe ts t 10 t 3 t 5 ack t 1 pci clk t 2 t 4 t 7 t 6 t 11 t 13 t 14 t 15 t 9 t 8 t 12
MPC5200B data sheet, rev. 3 freescale semiconductor 27 1.3.8.3 muxed mode notes: 1. ack can shorten the cs pulse width. wait states (ws) can be programmed in the chip select x regi ster, bit field waitp and waitx. it can be specified from 0 - 65535. 2. ack is input and can be used to shorten the cs pulse width. 3. deadcycles are only used, if no arbitration to an other module (ata or pci) of the shared local bus happens. if arbitration happens the bus can be driven within 4 ipb clocks by an other modules. table 26. muxed mode timing sym description min max units notes specid t csa pci clk to cs assertion 4.6 10.6 ns a7.39 t csn pci clk to cs negation 2.9 7.0 ns a7.40 t alea pci clk to ale assertion - 3.6 ns a7.41 t 1 ale assertion before address, bank, tsiz assertion - 5.7 ns a7.42 t 2 cs assertion before address, bank, tsiz negation - -1.2 ns a7.43 t 3 cs assertion before data wr valid - -1.2 ns a7.44 t 4 data wr hold after cs negation t ipbick - ns a7.45 t 5 data rd setup before cs negation 8.5 - ns a7.46 t 6 data rd hold after cs negation 0 (dc+1)*t pcick ns (1),(3) a7.47 t 7 ale pulse width - t pcick ns a7.48 t tsa cs assertion after ts assertion - 6.9 ns a7.49 t 8 ts pulse width - t pcick ns a7.50 t 9 cs pulse width (2+ws)*t pcick (2+ws)*t pcick ns a7.51 t oea oe assertion before cs assertion - 4.7 ns a7.52 t oen oe negation before cs negation - 5.9 ns a7.53 t 10 rw assertion before ale assertion t ipbick - ns a7.54 t 11 rw negation after cs negation - t pcick ns a7.55 t 12 ack assertion after cs assertion t ipbick -ns (2) a7.56 t 13 ack negation after cs negation - t pcick ns (2) a7.57 t 14 ale negation to cs assertion - t pcick ns a7.58 t 15 ack change before pci clock - 2.0 ns (2) a7.59 t 16 ack change after pci clock - 4.4 ns (2) a7.60
MPC5200B data sheet, rev. 3 28 freescale semiconductor figure 13. timing diagram?muxed mode 1.3.9 ata the MPC5200B ata controller is completely software programma ble. it can be programmed to operate with ata protocols using their respective timing, as describe d in the ansi ata-4 specification. the ata interface is completely asynchronous in nature. signal relationships are based on specific fixed timing in terms of timing units (nanoseconds). ata data setup and hold times, with respect to read/write str obes, are software programmable inside the ata controller. data setup and hold times are implemented using counters. the counters count the number of ata clock cycles needed to meet the ansi ata-4 timing specifications. for details , see the ansi ata-4 specification and how to program an ata controller and ata drive for different ata protocols and their respective timing. see the MPC5200B user manual. the MPC5200B ata host controller design makes data available coincidentally with the active edge of the write strobe in pio and multiword dma modes. ? write data is latched by the drive at the inactive edge of the write strobe. this gives ample setup-time beyond that required by the ata-4 specification. ? data is held unchanged until the next active edge of the write strobe. th is gives ample hold-time beyond that required by the ata-4 specification. pci clk ad[24:0] (wr) csx r/w ale ad[30:28] (wr) ad[26:25] (wr) ad[31,27] (wr) address[7:31] bank[0:1] bits tsiz[0:2] bits ack data data tenure address tenure ts data data data ad[31:0] (rd) data t 4 t 13 t 5 t 1 address latch t 7 t 6 t 11 t 9 t 12 t 10 t 8 t 2 t 3 oe t 14 t 15 t 16
MPC5200B data sheet, rev. 3 freescale semiconductor 29 all ata transfers are programmed in terms of system clock cycles (ip bus clocks) in the ata host controller timing registers. this puts constraints on the ata protocols and their respectiv e timing modes in which the at a controller can communicate with the drive. faster ata modes (i.e., udma 0, 1, 2) are supported when the sy stem is running at a sufficient frequency to provide adequate data transfer rates. adequate data tran sfer rates are a function of the following: ? the MPC5200B operating frequency (ip bus clock frequency) ? internal MPC5200B bus latencies ? other system load dependent variables the ata clock is the same frequency as the ip bu s clock in MPC5200B. see the MPC5200B user manual. note all output timing numbers are specified for nominal 50 pf loads. table 27. pio mode timing specifications sym pio timing parameter min/max (ns) mode 0 (ns) mode 1 (ns) mode 2 (ns) mode 3 (ns) mode 4 (ns) specid t 0 cycle time min 600 383 240 180 120 a8.1 t 1 address valid to dior /diow setup min 70 50 30 30 25 a8.2 t 2 dior /diow pulse width 16-bit 8-bit min min 165 290 125 290 100 290 80 80 70 70 a8.3 t 2i dior /diow recovery time min ? ? ? 70 25 a8.4 t 3 diow data setup min 60 45 30 30 20 a8.5 t 4 diow data hold min 30 20 15 10 10 a8.6 t 5 dior data setup min 50 35 20 20 20 a8.7 t 6 dior data hold min55555a8.8 t 9 dior /diow to address valid hold min2015101010a8.9 t a iordy setup max 35 35 35 35 35 a8.10 t b iordy pulse width max 1250 1250 1250 1250 1250 a8.11
MPC5200B data sheet, rev. 3 30 freescale semiconductor figure 14. pio mode timing table 28. multiword dma timing specifications sym multiword dma timing parameters min/max mode 0(ns) mode 1(ns) mode 2(ns) specid t 0 cycle time min 480 150 120 a8.12 t c dmack to dmarq delay max ? ? ? a8.13 t d dior /diow pulse width (16-bit) min 215 80 70 a8.14 t e dior data access max 150 60 50 a8.15 t g dior /diow data setup min 100 30 20 a8.16 t f dior data hold min 5 5 5 a8.17 t h diow data hold min 20 15 10 a8.18 t i dmack to dior /diow setup min 0 0 0 a8.19 t j dior /diow to dmack hold min 20 5 5 a8.20 t kr dior negated pulse width min 50 50 25 a8.21 t kw diow negated pulse width min 215 50 25 a8.22 t lr dior to dmarq delay max 120 40 35 a8.23 t lw diow to dmarq delay max 40 40 35 a8.24 wdata rdata iordy t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 9 t a t b cs [0]/cs [3]/da[2:0] dior /diow
MPC5200B data sheet, rev. 3 freescale semiconductor 31 figure 15. multiword dma timing note the direction of signal assertio n is towards the top of the page, and the direction of negation is towards the bottom of the page, irrespective of the electrical proper ties of the signal. table 29. ultra dma timing specification sym mode 0 (ns) mode 1 (ns) mode 2 (ns) comment specid min max min max min max t cyc 114 ? 75 ? 55 ? cycle time allowing for asymmetry and clock variations from strobe edge to strobe edge a8.26 t 2cyc 235 ? 156 ? 117 ? two-cycle time allowi ng for clock variations, from rising edge to next rising edge or from falling edge to next falling edge of strobe. a8.27 t ds 15 ? 10 ? 7 ? data setup time at recipient. a8.28 t dh 5?5?5? data hold time at recipient. a8.29 t dvs 70 ? 48 ? 34 ? data valid setup time at sender, to strobe edge. a8.30 t dvh 6 ? 6 ? 6 ? data valid hold time at sender, from strobe edge. a8.31 t fs 0 230 0 200 0 170 first strobe time for drive to first negate dstrobe from stop during a data-in burst. a8.32 t li 015001500150 limited interlock time. a8.33 t mli 20 ? 20 ? 20 ? interlock time with minimum. a8.34 t ui 0?0?0? unlimited interlock time. a8.35 t 0 t c t e t i t d t f t h t g t j dmarq rdata wdata (drive) (host) (host) (drive) (host) t l t k dmack dior diow
MPC5200B data sheet, rev. 3 32 freescale semiconductor notes: 1 t ui , t mli , t li indicate sender-to-recipient or recipient-to-sender interloc ks. that is, one agent (sender or recipient) is waiting for the other agent to respond with a signal before proceeding. ?t ui is an unlimited interlock that has no maximum time value. ?t mli is a limited time-out that has a defined minimum. ?t li is a limited time-out that has a defined maximum. 2 all timing parameters are measured at the connector of the driv e to which the parameter applies. for example, the sender shall stop generating strobe edges t rfs after negation of dmardy. strobe and dm ardy timing measurements are taken at the connector of the sender. even though the sender stops generating strobe edges, the receiver may receive additional strobe edges due to propagation delays. all timing measurement switching points (low to high and high to low) are taken at 1 . 5 v. t az ? 10 ? 10 ? 10 maximum time allowed for output drivers to release from being asserted or negated a8.36 t zah 20 ? 20 ? 20 ? minimum delay time required for output drivers to assert or negate from released state a8.37 t zad 0?0?0? a8.38 t env 20 70 20 70 20 70 envelope time?from dmack to stop and hdmardy during data out burst initiation. a8.39 t sr ? 50 ? 30 ? 20 strobe to dmardy time, if dmardy is negated before this long after strobe edge, the recipient receives no more than one additional data word. a8.40 t rfs ? 75 ? 60 ? 50 ready-to-final strobe time?no strobe edges are sent this long after negation of dmardy . a8.41 t rp 160 ? 125 ? 100 ? ready-to-pause time?the time recipient waits to initiate pause after negating dmardy . a8.42 t iordyz ? 20 ? 20 ? 20 pull-up time before allowing iordy to be released. a8.43 t ziordy 0 ? 0 ? 0 ? minimum time drive waits before driving iordy a8.44 t ack 20 ? 20 ? 20 ? setup and hold times for dmack , before assertion or negation. a8.45 t ss 50 ? 50 ? 50 ? time from strobe edge to negation of dmarq or assertion of stop, when sender terminates a burst. a8.46 table 29. ultra dma timing specification (continued) sym mode 0 (ns) mode 1 (ns) mode 2 (ns) comment specid min max min max min max
MPC5200B data sheet, rev. 3 freescale semiconductor 33 figure 16. timing diagram?initiating an ultra dma data in burst figure 17. timing diagram?sustained ultra dma data in burst t ui t ack t az t ack t ack t zad t fs t fs t env t env t ziordy t dvs t dvh t zad dmarq (device) dmack (device) stop (host) hdmardy (host) dstrobe (device) dd(0:15) da0, da1, da2, cs [0:1]1 t cyc dstrobe at host dstrobe at device dd(0:15) at device dd(0:15) at host t cyc t 2cyc t 2cyc t dvh t dvh t dvh t dvs t dvs t dh t dh t ds t ds t dh
MPC5200B data sheet, rev. 3 34 freescale semiconductor figure 18. timing diagram?host paus ing an ultra dma data in burst figure 19. timing diagram?drive termi nating ultra dma data in burst dmarq (device) t rp dmarq (host) stop (host) hdmardy (host) dstrobe (device) dd[0:15] (device) t rfs t sr dmarq (device) dmack (host) hdmardy (host) dstrobe (device) dd[0:15] t mli stop (host) da0, da1, da2, cs [0:1] t li t li t li t ack t ack t iordyz t ss t zah t az t dvs crc t ack t dvh
MPC5200B data sheet, rev. 3 freescale semiconductor 35 figure 20. timing diagram?host termi nating ultra dma data in burst figure 21. timing diagram?initiating an ultra dma data out burst dmarq (device) dmack (host) hdmardy (host) dstrobe (device) dd[0:15] t mli stop (host) da0, da1, da2, cs [0:1] t li t iordyz t az t ack t zah t rp t rfs t ack t li t dvs t dvh t ack crc t mli dmarq (device) dmack (host) ddmardy (host) hstrobe (device) dd[0:15] stop (host) da0, da1, da2, cs [0:1] t ack (host) t ui t ack t ack t li t ui t dvs t dvh t env t ziordy
MPC5200B data sheet, rev. 3 36 freescale semiconductor figure 22. timing diagram?sustai ned ultra dma data out burst figure 23. timing diagram?drive paus ing an ultra dma data out burst hstrobe (host) dd[0:15] (host) t cyc hstrobe (device) dd[0:15] (device) t cyc t 2cyc t 2cyc t dvh t dvs t dvs t dvh t dvh t dh t dh t dh t ds t ds dmarq (device) dmack (host) ddmardy hstrobe dd[0:15] stop (host) (host) (device) t sr t rfs t rp
MPC5200B data sheet, rev. 3 freescale semiconductor 37 figure 24. timing diagram?host termi nating ultra dma data out burst figure 25. timing diagram?drive termi nating ultra dma data out burst t li dmarq (device) dmack (host) ddmardy hstrobe dd[0:15] stop (host) da0, da1, da2, cs [0:1] (host) (device) (host) t mli t li t li t ack t ack t ack t dvs t dvh t iordyz t ss crc dmarq (device) dmack (host) ddmardy hstrobe dd[0:15] stop (host) da0, da1, da2, cs [0:1] (host) t ack t mli (device) (host) t li t mli t li t rp t rfs t ack t dvh t ack t dvs t iordyz crc
MPC5200B data sheet, rev. 3 38 freescale semiconductor figure 26. timing diagram-ata-isolation 1.3.10 ethernet ac test timing conditions: ? output loading all outputs: 25 pf figure 27. ethernet timing diagram?mii rx signal table 30. timing specification ata_isolation sym description min max units specid 1 ata_isolation setup ti me 7 - ip bus cycles a8.48 2 ata_isolation hold ti me - 19 ip bus cycles a8.49 table 31. mii rx signal timing sym description min max unit specid t 1 rxd[3:0], rx_dv, rx_er to rx_clk setup 10 ? ns a9.1 t 2 rx_clk to rxd[3:0], rx_dv, rx_er hold 10 ? ns a9.2 t 3 rx_clk pulse width high 35% 65% rx_clk period (1) 1 rx_clk shall have a frequency of 25% of data rate of the received signal. see th e ieee 802.3 specification. a9.3 t 4 rx_clk pulse width low 35% 65% rx_clk period ( 1) a9.4 dior 2 1 ata _ i s o l at i o n t 4 t 3 t 1 t 2 rx_clk (input) rxd[3:0] (inputs) rx_dv rx_er
MPC5200B data sheet, rev. 3 freescale semiconductor 39 figure 28. ethernet timi ng diagram?mii tx signal figure 29. ethernet timing diagram?mii async table 32. mii tx signal timing sym description min max unit specid t 5 tx_clk rising edge to txd[3:0], tx_en, tx_er invalid 5? ns a9.5 t 6 tx_clk rising edge to txd[3:0], tx_en, tx_er valid ? 25 ns a9.6 t 7 tx_clk pulse width high 35% 65% tx_clk period (1) 1 the tx_clk frequency shall be 25% of the nominal transmit frequency, e.g., a phy operating at 100 mb/s must provide a tx_clk frequency of 25 mhz and a phy operating at 10 mb/s must provide a tx_clk frequency of 2.5 mhz. see the ieee 802.3 specification. a9.7 t 8 tx_clk pulse width low 35% 65% tx_clk period (1) a9.8 table 33. mii async signal timing sym description min max unit specid t 9 crs, col minimum pulse width 1 . 5 ? tx_clk period a9.9 t 8 t 7 t 5 tx_clk (input) txd[3:0] (outputs) tx_en tx_er t 6 t 9 crs, col
MPC5200B data sheet, rev. 3 40 freescale semiconductor figure 30. ethernet timing di agram?mii serial management 1.3.11 usb note output timing is specified at a nominal 50 pf load. table 34. mii serial management channel signal timing sym description min max unit specid t 10 mdc falling edge to mdio output delay 0 25 ns a9.10 t 11 mdio (input) to mdc rising edge setup 10 ? ns a9.11 t 12 mdio (input) to mdc rising edge hold 10 ? ns a9.12 t 13 mdc pulse width high (1) 1 mdc is generated by MPC5200B with a duty cycle of 50% except when mii_speed in the fec mii_speed control register is changed during operation. see the MPC5200B user manual. 160 ? ns a9.13 t 14 mdc pulse width low (1) 160 ? ns a9.14 t 15 mdc period (2) 2 the mdc period must be set to a value of less than or equal to 2.5 mhz (to be compliant with the ieee mii characteristic) by programming the fec mii_speed c ontrol register. see the MPC5200B user manual. 400 ? ns a9.15 table 35. timing specifications?usb output line sym description min max units specid 1 usb bit width (1) 1 defined in the usb config register , (12 mbit/s or 1.5 mbit/s mode). 83.3 667 ns a10.1 2 transceiver enable time 83.3 667 ns a10.2 3 signal falling time ? 7.9 ns a10.3 4 signal rising time ? 7.9 ns a10.4 t 14 t 13 t 12 mdc (output) mdio (input) mdio (output) t 11 t 10 t 15
MPC5200B data sheet, rev. 3 freescale semiconductor 41 figure 31. timing diagram?usb output line 1.3.12 spi note output timing is specified at a nominal 50 pf load. table 36. timing specifications ? spi master mode, format 0 (cpha = 0) sym description min max units specid 1 cycle time 4 1024 ip-bus cycle (1) 1 inter peripheral clock is defined in the MPC5200B user manual. a11.1 2 clock high or low time 2 512 ip-bus cycle ( 1 ) a11.2 3 slave select to clock delay 15.0 ? ns a11.3 4 output data valid after slave select (ss ) ? 20.0 ns a11.4 5 output data valid after sck ? 20.0 ns a11.5 6 input data setup time 20.0 ? ns a11.6 7 input data hold time 20.0 ? ns a11.7 8 slave disable lag time 15.0 ? ns a11.8 9 sequential transfer delay 1 ? ip-bus cycle ( 1 ) a11.9 10 clock falling time ? 7.9 ns a11.10 11 clock rising time ? 7.9 ns a11.11 11 2 4 3 3 4 usb_oe usb_txn usb_txp
MPC5200B data sheet, rev. 3 42 freescale semiconductor figure 32. timing diagram ? spi master mode, format 0 (cpha = 0) note output timing is specified at a nominal 50 pf load. table 37. timing specifications ? spi slave mode, format 0 (cpha = 0) sym description min max units specid 1 cycle time 4 1024 ip-bus cycle (1) 1 inter peripheral clock is defined in the MPC5200B user manual. a11.12 2 clock high or low time 2 512 ip-bus cycle ( 1 ) a11.13 3 slave select to clock delay 15.0 ? ns a11.14 4 output data valid after slave select (ss ) ? 50.0 ns a11.15 5 output data valid after sck ? 50.0 ns a11.16 6 input data setup time 50.0 ? ns a11.17 7 input data hold time 0.0 ? ns a11.18 8 slave disable lag time 15.0 ? ns a11.19 9 sequential transfer delay 1 ? ip-bus cycle ( 1 ) a11.20 sck (clkpol=0) sck (clkpol=1) mosi output output output ss output miso input 1 22 8 9 3 4 5 6 6 7 7 11 10 10 11
MPC5200B data sheet, rev. 3 freescale semiconductor 43 figure 33. timing diagram ? spi slave mode, format 0 (cpha = 0) note output timing is specified at a nominal 50 pf load. table 38. timing specifications ? spi master mode, format 1 (cpha = 1) sym description min max units specid 1 cycle time 4 1024 ip-bus cycle (1) 1 inter peripheral clock is defined in the MPC5200B user manual. a11.21 2 clock high or low time 2 512 ip-bus cycle ( 1 ) a11.22 3 slave select to clock delay 15.0 ? ns a11.23 4 output data valid ? 20.0 ns a11.24 5 input data setup time 20.0 ? ns a11.25 6 input data hold time 20.0 ? ns a11.26 7 slave disable lag time 15.0 ? ns a11.27 8 sequential transfer delay 1 ? ip-bus cycle ( 1 ) a11.28 9 clock falling time ? 7.9 ns a11.29 10 clock rising time ? 7.9 ns a11.30 sck (clkpol=0) sck (clkpol=1) mosi input input input ss input miso output 1 22 9 3 7 4 6 5 8
MPC5200B data sheet, rev. 3 44 freescale semiconductor figure 34. timing diagram ? spi master mode, format 1 (cpha = 1) note output timing is specified at a nominal 50 pf load. table 39. timing specifications ? spi slave mode, format 1 (cpha = 1) sym description min max units specid 1 cycle time 4 1024 ip-bus cycle (1) 1 inter peripheral clock is defined in the MPC5200B user manual. a11.31 2 clock high or low time 2 512 ip-bus cycle ( 1 ) a11.32 3 slave select to clock delay 15.0 ? ns a11.33 4 output data valid ? 50.0 ns a11.34 5 input data setup time 50.0 ? ns a11.35 6 input data hold time 0.0 ? ns a11.36 7 slave disable lag time 15.0 ? ns a11.37 8 sequential transfer delay 1 ? ip-bus cycle ( 1 ) a11.38 sck (clkpol=0) sck (clkpol=1) mosi output output output ss output miso input 1 22 7 8 3 4 6 10 9 9 10 5
MPC5200B data sheet, rev. 3 freescale semiconductor 45 figure 35. timing diagram ? spi slave mode, format 1 (cpha = 1) 1.3.13 mscan the can functions are available as rx and tx pins at normal io pads (i 2 c1+gptimer or psc2). ther e is no filter for the wakeup dominant pulse. any high-to-low edge can cause wakeup, if configured. 1.3.14 i 2 c table 40. i 2 c input timing specifications?scl and sda sym description min max units specid 1 start condition hold time 2 ? ip-bus cycle (1) 1 inter peripheral clock is defined in the MPC5200B user manual. a13.1 2 clock low time 8 ? ip-bus cycle ( 1 ) a13.2 4 data hold time 0.0 ? ns a13.3 6 clock high time 4 ? ip-bus cycle ( 1 ) a13.4 7 data setup time 0.0 ? ns a13.5 8 start condition setup time (for repeated start condition only) 2 ? ip-bus cycle ( 1 ) a13.6 9 stop condition setup time 2 ? ip-bus cycle ( 1 ) a13.7 sck (clkpol=0) sck (clkpol=1) mosi input input input ss input miso output 1 22 7 8 3 4 6 5
MPC5200B data sheet, rev. 3 46 freescale semiconductor note output timing is specified at a nominal 50 pf load. figure 36. timing diagram?i 2 c input/output 1.3.15 j1850 see the MPC5200B user manual. table 41. i 2 c output timing specifications?scl and sda sym description min max units specid 1 (1) 1 programming ifdr with the maximum frequency (ifdr=0x20 ) results in the minimum output timings listed. the i 2 c interface is designed to scale the data transition time, moving it to the middle of t he scl low period. the actual position is affected by the prescale a nd division values programmed in ifdr. start condition hold time 6 ? ip-bus cycle ( 3 ) a13.8 2 ( 1 ) clock low time 10 ? ip-bus cycle ( 3 ) a13.9 3 (2) 2 because scl and sda are open-drain-type outputs, which the processor can only actively drive low, the time scl or sda takes to reach a high level depends on exte rnal signal capacitance and pull-up resistor values scl/sda rise time ? 7.9 ns a13.10 4 ( 1 ) data hold time 7 ? ip-bus cycle ( 3 ) a13.11 5 ( 1 ) scl/sda fall time ? 7.9 ns a13.12 6 ( 1 ) clock high time 10 ? ip-bus cycle ( 3 ) a13.13 7 ( 1 ) data setup time 2 ? ip-bus cycle ( 3 ) a13.14 8 ( 1 ) start condition setup time (for repeated start condition only) 20 ? ip-bus cycle ( 3 ) a13.15 9 ( 1 ) stop condition setup time 10 ? ip-bus cycle (3) 3 inter peripheral clock is defined in the MPC5200B user manual. a13.16 1 2 3 4 5 6 7 8 9 scl sda
MPC5200B data sheet, rev. 3 freescale semiconductor 47 1.3.16 psc 1.3.16.1 codec mode (8,16,24 and 32-bit)/i 2 s mode note output timing is specified at a nominal 50 pf load. figure 37. timing diagram ? 8, 16, 24, and 32-bit codec / i 2 s master mode table 42. timing specifications?8,16, 24, and 32-bit codec / i 2 s master mode sym description min typ max units specid 1 bit clock cycle time, programmed in ccs register 40.0 ? ? ns a15.1 2 clock duty cycle ? 50 ? % (1) 1 bit clock cycle time a15.2 3 bit clock fall time ? ? 7.9 ns a15.3 4 bit clock rise time ? ? 7.9 ns a15.4 5 framesync valid after clock edge ? ? 8.4 ns a15.5 6 framesync invalid after clock edge ? ? 8.4 ns a15.6 7 output data valid after clock edge ? ? 9.3 ns a15.7 8 input data setup time 6.0 ? ? ns a15.8 bitclk 5 3 4 3 4 (clkpol=0) bitclk (clkpol=1) framesync (syncpol = 1) txd output output output 6 7 8 output framesync (syncpol = 0) output rxd input 1 22
MPC5200B data sheet, rev. 3 48 freescale semiconductor note output timing is specified at a nominal 50 pf load. figure 38. timing diagram ? 8,16, 24, and 32-bit codec / i 2 s slave mode table 43. timing specifications ? 8,16, 24, and 32-bit codec / i 2 s slave mode sym description min typ max units specid 1 bit clock cycle time 40.0 ? ? ns a15.9 2 clock duty cycle ? 50 ? % (1) 1 bit clock cycle time a15.10 3 framesync setup time 1.0 ? ? ns a15.11 4 output data valid after clock edge ? ? 14.0 ns a15.12 5 input data setup time 1.0 ? ? ns a15.13 6 input data hold time 1.0 ? ? ns a15.14 bitclk 3 (clkpol=0) bitclk (clkpol=1) framesync (syncpol = 1) txd output input input 4 5 input framesync (syncpol = 0) input rxd input 1 22 6
MPC5200B data sheet, rev. 3 freescale semiconductor 49 1.3.16.2 ac97 mode note output timing is specified at a nominal 50 pf load. figure 39. timing diagram ? ac97 mode 1.3.16.3 irda mode note output timing is specified at a nominal 50 pf load. table 44. timing specifications ? ac97 mode sym description min typ max units specid 1 bit clock cycle time ? 81.4 ? ns a15.15 2 clock pulse high time ? 40.7 ? ns a15.16 3 clock pulse low time ? 40.7 ? ns a15.17 4 framesync valid after rising clock edge ? ? 13.0 ns a15.18 5 output data valid after rising clock edge ? ? 14.0 ns a15.19 6 input data setup time 1.0 ? ? ns a15.20 7 input data hold time 1.0 ? ? ns a15.21 table 45. timing specifications ? irda transmit line sym description min max units specid 1 pulse high time, defined in the irda protocol definition 0.125 10000 s a15.22 2 pulse low time, defined in the irda protocol definition 0.125 10000 s a15.23 3 transmitter rising time ? 7.9 ns a15.24 4 transmitter falling time ? 7.9 ns a15.25 bitclk (clkpol=0) framesync (syncpol = 1) sdata_out output input 6 output sdata_in input 1 4 3 5 2 7
MPC5200B data sheet, rev. 3 50 freescale semiconductor figure 40. timing diagram ? irda transmit line 1.3.16.4 spi mode note output timing is specified at a nominal 50 pf load. table 46. timing specifications ? spi master mode, format 0 (cpha = 0) sym description min max units specid 1 sck cycle time, programable in the psc ccs register 30.0 ? ns a15.26 2 sck pulse width, 50% sck duty cycle 15.0 ? ns a15.27 3 slave select clock delay, programable in the psc ccs register 30.0 ? ns a15.28 4 output data valid after slave select (ss ) ? 8.9 ns a15.29 5 output data valid after sck ? 8.9 ns a15.30 6 input data setup time 6.0 ? ns a15.31 7 input data hold time 1.0 ? ns a15.32 8 slave disable lag time ? 8.9 ns a15.33 9 sequential transfer delay, programable in the psc ctur / ctlr register 15.0 ? ns a15.34 10 clock falling time ? 7.9 ns a15.35 11 clock rising time ? 7.9 ns a15.36 irda_tx 4 3 (sir / fir / mir) 12
MPC5200B data sheet, rev. 3 freescale semiconductor 51 figure 41. timing diagram ? spi master mode, format 0 (cpha = 0) note output timing is specified at a nominal 50 pf load. table 47. timing specifications ? spi slave mode, format 0 (cpha = 0) sym description min max units specid 1 sck cycle time, programable in the psc ccs register 30.0 ? ns a15.37 2 sck pulse width, 50% sck duty cycle 15.0 ? ns a15.38 3 slave select clock delay 1.0 ? ns a15.39 4 input data setup time 1.0 ? ns a15.40 5 input data hold time 1.0 ? ns a15.41 6 output data valid after ss ? 14.0 ns a15.42 7 output data valid after sck ? 14.0 ns a15.43 8 slave disable lag time 0.0 ? ns a15.44 9 minimum sequential transfer delay = 2 * ip bus clock cycle time 30.0 ? ? a15.45 sck (clkpol=0) sck (clkpol=1) mosi output output output ss output miso input 1 22 8 9 3 4 5 6 6 7 7 11 10 10 11
MPC5200B data sheet, rev. 3 52 freescale semiconductor figure 42. timing diagram ? spi slave mode, format 0 (cpha = 0) note output timing is specified at a nominal 50 pf load. table 48. timing specifications ? spi master mode, format 1 (cpha = 1) sym description min max units specid 1 sck cycle time, programable in the psc ccs register 30.0 ? ns a15.46 2 sck pulse width, 50% sck duty cycle 15.0 ? ns a15.47 3 slave select clock delay, programable in the psc ccs register 30.0 ? ns a15.48 4 output data valid ? 8.9 ns a15.49 5 input data setup time 6.0 ? ns a15.50 6 input data hold time 1.0 ? ns a15.51 7 slave disable lag time ? 8.9 ns a15.52 8 sequential transfer delay, programable in the psc ctur / ctlr register 15.0 ? ns a15.53 9 clock falling time ? 7.9 ns a15.54 10 clock rising time ? 7.9 ns a15.55 sck (clkpol=0) sck (clkpol=1) mosi input input input ss input miso output 1 22 9 3 7 4 6 5 8
MPC5200B data sheet, rev. 3 freescale semiconductor 53 figure 43. timing diagram ? spi master mode, format 1 (cpha = 1) note output timing is specified at a nominal 50 pf load. table 49. timing specifications ? spi slave mode, format 1 (cpha = 1) sym description min max units specid 1 sck cycle time, programable in the psc ccs register 30.0 ? ns a15.56 2 sck pulse width, 50% sck duty cycle 15.0 ? ns a15.57 3 slave select clock delay 0.0 ? ns a15.58 4 output data valid ? 14.0 ns a15.59 5 input data setup time 2.0 ? ns a15.60 6 input data hold time 1.0 ? ns a15.61 7 slave disable lag time 0.0 ? ns a15.62 8 minimum sequential transfer delay = 2 * ip-bus clock cycle time 30.0 ? ns a15.63 sck (clkpol=0) sck (clkpol=1) mosi output output output ss output miso input 1 22 7 8 3 4 6 10 9 9 10 5
MPC5200B data sheet, rev. 3 54 freescale semiconductor figure 44. timing diagram ? spi slave mode, format 1 (cpha = 1) 1.3.17 gpios and timers 1.3.17.1 general and asynchronous signals the MPC5200B contains several sets if i/os that do not require special setup, hold, or valid requirements. most of these are asynchronous to the system clock. the following numbers are pr ovided for test and validation purposes only, and they assume a 133 mhz internal bus frequency. figure 45 shows the gpio timing diagram. table 50 gives the timing specifications. table 50. asynchronous signals sym description min max units specid t ck clock period 7.52 ? ns a16.1 t is input setup 12 ? ns a16.2 t ih input hold 1 ? ns a16.3 t dv output valid ? 15.33 ns a16.4 t dh output hold 1 ? ns a16.5 sck (clkpol=0) sck (clkpol=1) mosi input input input ss input miso output 1 22 7 8 3 4 6 5
MPC5200B data sheet, rev. 3 freescale semiconductor 55 figure 45. timing diagram?asynchronous signals output input t ck valid valid t dv t dh t is t ih
MPC5200B data sheet, rev. 3 56 freescale semiconductor 1.3.18 ieee 1149.1 (jtag) ac specifications figure 46. timing diag ram?jtag clock input figure 47. timing diagram?jtag trst table 51. jtag timing specification sym characteristic min max unit specid ? tck frequency of operation. 0 25 mhz a17.1 1 tck cycle time. 40 ? ns a17.2 2 tck clock pulse width measured at 1.5v. 1 . 08 ? ns a17.3 3 tck rise and fall times. 0 3 ns a17.4 4trst setup time to tck falling edge (1) . 1 trst is an asynchronous signal. the setup time is for test purposes only. 10 ? ns a17.5 5trst assert time. 5 ? ns a17.6 6 input data setup time (2) . 2 non-test, other than tdi and tms, signal input timing with respect to tck. 5 ? ns a17.7 7 input data hold time ( 2 ) . 15 ? ns a17.8 8 tck to output data valid (3) . 3 non-test, other than tdo, signal ou tput timing with respect to tck. 030nsa17.9 9 tck to output high impedance ( 3 ) . 0 30 ns a17.10 10 tms, tdi data setup time. 5 ? ns a17.11 11 tms, tdi data hold time. 1 ? ns a17.12 12 tck to tdo data valid. 0 15 ns a17.13 13 tck to tdo high impedance. 0 15 ns a17.14 tck vm vm vm 3 3 22 1 vm = midpoint voltage numbers shown reference table 51 . tck trst 5 4 numbers shown reference table 51 .
MPC5200B data sheet, rev. 3 freescale semiconductor 57 figure 48. timing diagram?jtag boundary scan figure 49. timing diagram?test access port 2 package description 2.1 package parameters the MPC5200B uses a 27 mm x 27 mm te-pbga package. the package parameters are as provided in the following list: ? package outline: 27 mm x 27 mm ? interconnects: 2 ? pitch: 1.27 mm tck input data valid output data valid data inputs data outputs data outputs 6 7 8 9 numbers shown reference table 51 . tck input data valid output data valid tdi, tms tdo tdo 10 11 12 13 numbers shown reference table 51 .
MPC5200B data sheet, rev. 3 58 freescale semiconductor 2.2 mechanical dimensions figure 50 provides the mechanical dimensions, top surface, si de profile, and pinout for the MPC5200B, 272 te-pbga package. figure 50. mechanical dimensions and pinout assignments for the MPC5200B, 272 te-pbga case 1135a?01 issue b date 10/15/1997 c b dim min max millimeters a 2.05 2.65 a1 0.50 0.70 a2 0.50 0.70 a3 1.05 1.25 b 0.60 0.90 d 27.00 bsc d1 24.13 ref d2 23.30 24.70 e 27.00 bsc e1 24.13 ref e2 23.30 24.70 e 1.27 bsc notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension is measured at the maximum solder ball diameter parallel to primary datum a. 4. primary datum a and the seating plane are defined by the spherical crowns of the solder balls. pin a1 e2 d2 d e b m 0.2 index c 0.2 4x top view (d1) a (e1) 4x e 19x e /2 19x e 123 5 4 678910111213141516171819 a b c d e f g h j k l m n p r t u 20 v w y 272x b 3 c b m 0.3 a m 0.15 a side view 0.35 a a 0.2 a 272x a bottom view a2 a1 a3
MPC5200B data sheet, rev. 3 freescale semiconductor 59 2.3 pinout listings see details in the MPC5200B user manual. table 52. MPC5200B pinout listing name alias type power supply output driver type input type pull-up/ down sdram mem_cas cas i/o vdd_mem_io drv16_mem ttl mem_clk_en clk_en i/o vdd_mem_io drv16_mem ttl mem_cs i/o vdd_mem_io drv16_mem ttl mem_dqm[3:0] dqm i/o vdd_mem_io drv16_mem ttl mem_ma[12:0] ma i/o vdd_mem_io drv16_mem ttl mem_mba[1:0] mba i/o vdd_mem_io drv16_mem ttl mem_mdqs[3:0] mdqs i/o vdd_mem_io drv16_mem ttl mem_mdq[31:0] mdq i/o vdd_mem_io drv16_mem ttl mem_clk i/o vdd_mem_io drv16_mem ttl mem_clk i/o vdd_mem_io drv16_mem ttl mem_ras ras i/o vdd_mem_io drv16_mem ttl mem_we i/o vdd_mem_io drv16_mem ttl pci ext_ad[31:0] i/o vdd_io pci pci pci_cbe_0 i/o vdd_io pci pci pci_cbe_1 i/o vdd_io pci pci pci_cbe_2 i/o vdd_io pci pci pci_cbe_3 i/o vdd_io pci pci pci_clock i/o vdd_io pci pci pci_devsel i/o vdd_io pci pci pci_frame i/o vdd_io pci pci pci_gnt i/o vdd_io drv8 ttl pci_idsel i/o vdd_io drv8 ttl pci_irdy i/o vdd_io pci pci pci_par i/o vdd_io pci pci pci_perr i/o vdd_io pci pci pci_req i/o vdd_io drv8 ttl pci_reset i/o vdd_io pci pci pci_serr i/o vdd_io pci pci pci_stop i/o vdd_io pci pci
MPC5200B data sheet, rev. 3 60 freescale semiconductor pci_trdy i/o vdd_io pci pci local plus lp_ack i/o vdd_io drv8 ttl pullup lp_ale i/o vdd_io drv8 ttl lp_oe i/o vdd_io drv8 ttl lp_rw i/o vdd_io drv8 ttl lp_ts i/o vdd_io drv8 ttl lp_cs0 i/o vdd_io drv8 ttl lp_cs1 i/o vdd_io drv8 ttl lp_cs2 i/o vdd_io drv8 ttl lp_cs3 i/o vdd_io drv8 ttl lp_cs4 i/o vdd_io drv8 ttl lp_cs5 i/o vdd_io drv8 ttl ata ata_dack i/o vdd_io drv8 ttl ata_drq i/o vdd_io drv8 ttl pulldown ata_intrq i/o vdd_io drv8 ttl pulldown ata_iochrdy i/o vdd_io drv8 ttl pullup ata_ior i/o vdd_io drv8 ttl ata_iow i/o vdd_io drv8 ttl ata_isolation i/o vdd_io drv8 ttl ethernet eth_0 tx, tx_en i/o vdd_io drv4 ttl eth_1 rts, txd[0] i/o vdd_io drv4 ttl eth_2 usb_txp, rtx, txd[1] i/o vdd_io drv4 ttl eth_3 usb_prtpwr, txd[2] i/o vdd_io drv4 ttl eth_4 usb_speed, txd[3] i/o vdd_io drv4 ttl eth_5 usb_supend, tx_er i/o vdd_io drv4 ttl eth_6 usb_oe, rts, mdc i/o vdd_io drv4 ttl eth_7 txn, mdio i/o vdd_io drv4 ttl table 52. MPC5200B pinout listing (continued) name alias type power supply output driver type input type pull-up/ down
MPC5200B data sheet, rev. 3 freescale semiconductor 61 eth_8 rx_dv i/o vdd_io drv4 ttl eth_9 cd, rx_clk i/o vdd_io drv4 schmitt eth_10 cts, col i/o vdd_io drv4 ttl eth_11 tx_clk i/o vdd_io drv4 schmitt eth_12 rxd[0] i/o vdd_io drv4 ttl eth_13 usb_rxd, cts, rxd[1] i/o vdd_io drv4 ttl eth_14 usb_rxp, uart_rx, rxd[2] i/o vdd_io drv4 ttl eth_15 usb_rxn, rx, rxd[3] i/o vdd_io drv4 ttl eth_16 usb_ovrcnt, cts, rx_er i/o vdd_io drv4 ttl eth_17 cd, crs i/o vdd_io drv4 ttl irda psc6_0 irda_rx, rxd i/o vdd_io drv4 ttl psc6_1 frame, cts i/o vdd_io drv4 ttl psc6_2 irda_tx, txd i/o vdd_io drv4 ttl psc6_3 ir_usb_clk,bitc lk, rts i/o vdd_io drv4 schmitt usb usb_0 usb_oe i/o vdd_io drv4 ttl usb_1 usb_txn i/o vdd_io drv4 ttl usb_2 usb_txp i/o vdd_io drv4 ttl usb_3 usb_rxd i/o vdd_io drv4 ttl usb_4 usb_rxp i/o vdd_io drv4 ttl usb_5 usb_rxn i/o vdd_io drv4 ttl usb_6 usb_prtpwr i/o vdd_io drv4 ttl usb_7 usb_speed i/o vdd_io drv4 ttl usb_8 usb_supend i/o vdd_io drv4 ttl usb_9 usb_ovrcnt i/o vdd_io drv4 ttl i 2 c i2c_0 scl i/o vdd_io drv4 schmitt i2c_1 sda i/o vdd_io drv4 schmitt i2c_2 scl i/o vdd_io drv4 schmitt table 52. MPC5200B pinout listing (continued) name alias type power supply output driver type input type pull-up/ down
MPC5200B data sheet, rev. 3 62 freescale semiconductor i2c_3 sda i/o vdd_io drv4 schmitt psc psc1_0 txd, sdata_out, mosi, tx i/o vdd_io drv4 ttl psc1_1 rxd, sdata_in, miso, tx i/o vdd_io drv4 ttl psc1_2 mclk, sync, rts i/o vdd_io drv4 ttl psc1_3 bitclk, sck, cts i/o vdd_io drv4 schmitt psc1_4 frame, ss , cd i/o vdd_io drv4 ttl psc2_0 txd, sdata_out, mosi, tx i/o vdd_io drv4 ttl psc2_1 rxd, sdata_in, miso, tx i/o vdd_io drv4 ttl psc2_2 mclk, sync, rts i/o vdd_io drv4 ttl psc2_3 bitclk, sck, cts i/o vdd_io drv4 schmitt psc2_4 frame, ss , cd i/o vdd_io drv4 ttl psc3_0 usb_oe, txds, tx i/o vdd_io drv4 ttl psc3_1 usb_txn, rxd, rx i/o vdd_io drv4 ttl psc3_2 usb_txp, bitclk, rts i/o vdd_io drv4 schmitt psc3_3 usb_rxd, frame, ss , cts i/o vdd_io drv4 ttl psc3_4 usb_rxp, cd i/o vdd_io drv4 ttl psc3_5 usb_rxn i/o vdd_io drv4 ttl psc3_6 usb_prtpwr, mclk, mosi i/o vdd_io drv4 ttl psc3_7 usb_speed. miso i/o vdd_io drv4 ttl psc3_8 usb_supend, ss i/o vdd_io drv4 ttl psc3_9 usb_ovrcnt, sck i/o vdd_io drv4 ttl gpio/timer gpio_wkup_6 mem_cs1 i/o vdd_mem_io drv16_mem ttl pullup_mem gpio_wkup_7 i/o vdd_io drv8 ttl timer_0 i/o vdd_io drv4 ttl table 52. MPC5200B pinout listing (continued) name alias type power supply output driver type input type pull-up/ down
MPC5200B data sheet, rev. 3 freescale semiconductor 63 timer_1 i/o vdd_io drv4 ttl timer_2 mosi i/o vdd_io drv4 ttl timer_3 miso i/o vdd_io drv4 ttl timer_4 ss i/o vdd_io drv4 ttl timer_5 sck i/o vdd_io drv4 ttl timer_6 i/o vdd_io drv4 ttl timer_7 i/o vdd_io drv4 ttl clock sys_xtal_in input vdd_io sys_xtal_out output vdd_io rtc_xtal_in input vdd_io rtc_xtal_out output vdd_io misc porreset input vdd_io drv4 schmitt hreset i/o vdd_io drv8_od 1 schmitt sreset i/o vdd_io drv8_od 1 schmitt irq0 i/o vdd_io drv4 ttl irq1 i/o vdd_io drv4 ttl irq2 i/o vdd_io drv4 ttl irq3 i/o vdd_io drv4 ttl test/configuration sys_pll_tpa i/o vdd_io drv4 ttl test_mode_0 input vdd_io drv4 ttl test_mode_1 input vdd_io drv4 ttl test_sel_0 i/o vdd_io drv4 ttl pullup test_sel_1 i/o vdd_io drv8 ttl jtag_tck tck input vdd_io drv4 schmitt pullup jtag_tdi tdi input vdd_io drv4 ttl pullup jtag_tdo tdo i/o vdd_io drv8 ttl jtag_tms tms input vdd_io drv4 ttl pullup jtag_trst trst input vdd_io drv4 ttl pullup power and ground vdd_io - table 52. MPC5200B pinout listing (continued) name alias type power supply output driver type input type pull-up/ down
MPC5200B data sheet, rev. 3 64 freescale semiconductor 3 system design information 3.1 power up/down sequencing figure 51 shows situations in sequencing the i/o v dd (vdd_io), memory vdd (vdd_io_mem), pll vdd (pll_avdd), and core vdd (vdd_core). figure 51. supply voltage sequencing vdd_mem_io - vdd_core - vss_io/core - sys_pll_avdd - core_pll_avdd - 1 all ?open drain? outputs of the mpc5200 b are actually regular thr ee-state output drivers with the output data tied low and the output enable controlled. thus, unlike a true open drain, there is a current path from the external system to the MPC5200B i/o power rail if the external signal is driven above the MPC5200B i/o power rail voltage. table 52. MPC5200B pinout listing (continued) name alias type power supply output driver type input type pull-up/ down 1.5v 2.5v 3.3v 0 dc power supply voltage vdd_io, vdd_io_mem (sdr) vdd_io_mem (ddr) vdd_core, pll_avdd note: vdd_core should not exceed vdd_io, vdd_io_mem or p ll_avdd by more than 0.4 v at any time, including power-up. note: it is recommended that vdd_core/pll_avdd should track vdd_io/vdd_io_mem up to 0.9 v then separate for completion of ramps. note: input voltage must not be greater than the supply voltage (vdd_io) vdd_io_mem, vdd_core, or pll_avdd) by more than 0.5 v at any time, including during power-up. note: use 1 microsecond or slower rise time for all supplies. 1 2 time
MPC5200B data sheet, rev. 3 freescale semiconductor 65 the relationship between vdd_io_mem and vdd_io is non-critical during power-up and power-down sequences. vdd_io_mem (2.5 v or 3.3 v) and vdd_io are specified relative to vdd_core. 3.1.1 power up sequence if vdd_io/vdd_io_mem are powered up with the vdd_core at 0v , the sense circuits in the i/o pads cause all pad output drivers connected to the vdd_io/vdd_io_mem to be in a high-impedance state. there is no limit to how long after vdd_io/vdd_io_mem powers up before vdd_core must power up. vdd_core should not lead the vdd_io, vdd_io_mem or pll_avdd by more than 0.4 v during power ramp up or there will be high current in the internal esd protection diodes. the rise times on the power supplies should be slower than 1 microsecond to avoid turning on the internal esd protection clamp diodes. the recommended power up sequence is as follows: use one microsecond or slower rise time for all supplies. vdd_core/pll_avdd and vdd_io/vdd_io_mem should track up to 0.9 v and then separate for the completion of ramps with vdd_io/vdd_io_mem go ing to the higher extern al voltages. one way to accomplish this is to use a low drop-out voltage regulator. 3.1.2 power down sequence if vdd_core/pll_avdd are powered down first, sense circuits in the i/o pads cause all output drivers to be in a high impedance state. there is no limit on how long after vdd_core and pll_avdd power down before vdd_io or vdd_io_mem must power down. vdd_core should not lag vdd_io, vdd_io_mem, or pll_avdd going low by more than 0.5v during power down or there will be undesired high current in the esd protection diodes. there are no requirements for the fall times of the power supplies. the recommended power down sequence is as follows: 1. drop vdd_core/pll_avdd to 0v. 2. drop vdd_io/vdd_io_mem supplies. 3.2 system and cpu core avdd power supply filtering each of the independent pll power supplies require filtering external to the device. the following drawing is a recommendation for the required filter circuit. figure 52. power supply filtering 3.3 pull-up/pull-down resistor requirements the MPC5200B requires external pull-up or pull-down resistors on certain pins. 3.3.1 pull-down resistor requirements for test pins the MPC5200B requires pull-down resistors on the te st pins test_mode_0, tes t_mode_1, test_sel_1. avdd device pin power supply source < 1 w 10 w 200-400 pf 10 mf
MPC5200B data sheet, rev. 3 66 freescale semiconductor 3.3.2 pull-up requirements for the pci control lines if the pci interface is not used (and internally disabled) the pc i control pins must be terminat ed as indicated by the pci loca l bus specification. this is also required for most/graphics and large flash mode. pci control signals always require pull-up resistors on the moth erboard (not the expansion board) to ensure that they contain stable values when no agent is activel y driving the bus. this includes pci_frame, pci_trdy, pci_irdy, pci_devsel, pci_stop, pci_serr, pci_perr, and pci_req. 3.3.3 pull-up/pull-down requiremen ts for mem_mdqs pins (sdram) the mem_mdqs[3:0] signals are not used with sdr memories and require pull-up or pull-down resistors in sdram mode. 3.3.4 . pull-up/pull-down requirements fo r mem_mdqs pins (ddr 16-bit mode) the mem_mdqs[1:0] signals are not used in ddr 16-bit mode and require pull-down resistors. 3.4 jtag the MPC5200B provides the user an ieee 1149.1 jtag interface to facilitate board/system testing. it also provides a common on-chip processor (cop) interface, which shares the ieee 1149.1 jtag port. the cop in terface provides access to the MPC5200B's embedded freescale (formerly motorola) mpc603e e300 processor. this interface provides a means for executing test routines and for performing software development and debug functions. 3.4.1 jtag_trst boundary scan testing is enabled through the jtag interface si gnals. the jtag_trst signal is optional in the ieee 1149.1 specification but is provided on all processors that implement the powerpc architecture. to obtain a reliable power-on reset performance, the jtag_trst signal must be asserted during power-on reset. 3.4.1.1 jtag_trst and porreset the jtag interface can control the direction of the MPC5200B i/ o pads via the boundary scan chain. the jtag module must be reset before the MPC5200B comes out of power-on reset; do this by asserting jtag_trst before porreset is released. for more details refer to the reset and jtag timing specification. figure 53. porreset vs. jtag_trst 3.4.1.2 connecting jtag_trst the wiring of the jtag_trst depends on the existence of a boar d-related debug interface. (see below) jtag_trst porreset required assertion of jtag_trst optional assertion of jtag_trst
MPC5200B data sheet, rev. 3 freescale semiconductor 67 normally this interface is implemented, using a cop (commo n on-chip processor) connector. the cop allows a remote computer system (typically , a pc with dedicated hardware and debugging soft ware) to access and control the internal operations of the MPC5200B. 3.4.2 e300 cop/bdm interface there are two possibilities to connect the jtag interface: us ing it with a cop connector and without a cop connector. 3.4.2.1 boards interfacing the jtag port via a cop connector the MPC5200B functional pin interface and internal logic provi des access to the embedded e300 processor core through the freescale (formerly motorola) standard cop/bdm interface. table 53 gives the cop/bdm interface signals. the pin order shown reflects only the cop/bdm connector order. for a board with a cop (commo n on-chip processor) connector , which accesses the jtag interface and which needs to reset the jtag module, simply wiring jtag_trst and porreset is not recommended. table 53. cop/bdm interface signals bdm pin # MPC5200B i/o pin bdm connector internal pull up/down external pull up/down i/o 1 1 with respect to the emulator tool?s perspec tive, input is really an output from the embedded e300 core and output is really an input to the core. 16 ? gnd ? ? ? 15 test_sel_0 ckstp_out ? ? i 14 ? key ? ? ? 13 hreset hreset 10k pull-up o 12 ? gnd ? ? ? 11 sreset sreset 10k pull-up o 10 ? n/c ? ? ? 9 jtag_tms tms 100k pull-up 10k pull-up o 8? n/c ? ?? 7 jtag_tck tck 100k pull-up 10k pull-up o 6? vdd 2 2 from the board under test, power sense for chip power. ??? 5 ? halted 3 3 halted is not available from e300 core. ??i 4 jtag_trst trst 100k pull-up 10k pull-up o 3 jtag_tdi tdi 100k pull-up 10k pull-up o 2 ? qack 4 4 input to the e300 core to enable/disable soft -stop condition during breakpoints. MPC5200B internally ties core_qack to gnd in its normal/functional mode (always asserted). ??o 1jtag_tdo tdo ? ? i
MPC5200B data sheet, rev. 3 68 freescale semiconductor to reset the MPC5200B via the cop connector, the hreset pin of the cop should be connected to the hreset pin of the MPC5200B. the circuitry shown in figure 54 allows the cop to assert hreset or jtag_trst separately, while any other board sources can drive porreset . figure 54. cop connector diagram 3.4.2.2 boards without cop connector if the jtag interface is not used, jtag_trst should be tied to porreset , so that it is asserted wh en the system reset signal (porreset ) is asserted. this ensures that the jtag scan chain is initia lized during power on. figure 55 shows the connection of the jtag interface without cop connector. 1 3 5 7 9 11 13 15 2 4 6 8 10 12 k 16 key key 14 hreset sreset vdd vdd jtag_trst vdd jtag_tms vdd jtag_tck vdd jtag_tdi test_sel_0 jtag_tdo 3 11 16 4 9 12 7 6 (2) 15 1 10 8 5 (3) 2 (4) 13 nc nc nc nc tdo hreset sreset trst tms tck tdi ckstp_out vdd 10kohm 10kohm 10kohm 10kohm 10kohm cop header cop connector physical pinout halted qack MPC5200B vdd 10kohm porreset porreset
MPC5200B data sheet, rev. 3 freescale semiconductor 69 figure 55. jtag_trst wiring for boards without cop connector 4 ordering information table 54. ordering information part number 1 1 shipped in trays. add ?r2? suffix for tape & reel. speed ambient temp qualification 2 2 commercial qualified to <250ppm level. industrial/automotive qualified to aec-q100. automotive has zero defect flow. packaging 3 3 standard is halide-free with pb solder balls. mpc5200vr400b 400 0c to 70c commercial rohs & pb-free mpc5200cvr466b 400 -40c to 85c industrial rohs & pb-free spc5200vvr266b 266 -40c to 105c automotive ? aec rohs & pb-free spc5200cbv400b 400 -40c to 85c automotive ? aec standard spc5200cvr400b 400 -40c to 85c automotive ? aec rohs & pb-free hreset sreset vdd vdd jtag_trst vdd jtag_tms vdd jtag_tck vdd jtag_tdi test_sel_0 jtag_tdo hreset sreset 10kohm 10kohm MPC5200B porreset porreset 10kohm 10kohm 10kohm
MPC5200B data sheet, rev. 3 70 freescale semiconductor 5 document revision history table 55 provides a revision history for this hardware specification. table 55. document revision history rev. no. differences 1 clock frequencies table: 466 mhz was changed to 400 mhz for the e300 processor core 2 added description for pci clk slew rate for pci clk specifications table. added description for minimum rates in t he ddr sdram memory write timing table. 3 added one item to table ?ddr sdram memory read timing.?
MPC5200B data sheet, rev. 3 freescale semiconductor 71 this page intentionally blank
document number: MPC5200Bds rev. 3 10/2008 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2008. all rights reserved.

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